Modern high-density integrated circuits (ICs) are known to be vulnerable to damage from ESD from a charged body (human or otherwise) as the charged body physically contacts the IC. ESD damage occurs when the amount of charge exceeds the capability of the electrical conduction path through the IC. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting in the metal-oxide-semiconductor (MOS) context.
An IC may be subjected to a damaging ESD event in the manufacturing process, during assembly, testing, or in the system application. In conventional IC ESD protection schemes, active clamp circuits are generally used to shunt ESD current between the power supply rails and thereby protect internal IC element nodes that are connected to bond pads from ESD damage.
One type of active ESD clamp circuit, known as an active Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell (active FET ESD cell), typically includes a trigger circuit coupled between the power supply rails that has a trigger output that couples to a gate of a large area MOSFET clamp transistor which acts as a shunting circuit being in parallel to the pin(s) being protected when triggered ON. The conduction of the clamp transistor(s) is controlled by the trigger circuit.
One known active FET based active ESD cell arrangement is based on a large area high-voltage MOS device (e.g. drain extended MOS (DEMOS), or laterally diffused MOS (LDMOS)). This arrangement has the negative attribute of consuming a large area because the entire ESD current (typically about 1.5 A) must be carried in the normal MOS mode (typically few hundred μA/μm width). Such an active FET may comprise a PMOS, NMOS, or a bipolar junction transistor (BJT) using a different trigger circuit.
Another known active FET based active ESD cell arrangement is obtained by stacking two or more lower voltage ESD cells in series between the power supply rails. This arrangement increases the trigger voltage rating of the ESD protection circuit, such as by a factor of 2 for two series stacked ESD cells. This arrangement has the advantage of consuming less area, but suffers because the series combination increases all voltages by the same ratio. Thus, the headroom (i.e. the difference between the trigger-voltage and the normal operating voltage) is increased beyond what would be necessary for a single ESD cell design. Series ESD cells in this arrangement require that each ESD cell reach the voltage at which trigger current flows before any one ESD cell can trigger.